In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
TSMC: https://www.tsmc.com/english/dedicatedFoundry/technology/log...
Not sure what this source is, but it looks sketchy.
In simpler terms, the SRAM density improved by 2.9% (according to ChatGPT). Which is better than it sounds, because SRAM had reached a wall, in terms of density gains, and, chips can be dominated by SRAM in terms of surface area, so this can mean a lot more room for logic, even though that is also getting considerably denser.
There's some hope of smaller SRAM in the future - https://raaam-tech.com/technology/ is a three-transistor SRAM.
It's not quite SRAM, it needs to be refreshed like DRAM. That's the main downside compared to SRAM but it's still very interesting.
Chip density increase is slowing down. Since N10, density scaling has been 60-80%. N3 to N2 is only 20%. And now N2 to A14 is also only 20%.
A lot of that is the lack of SRAM scaling. There’s still quite a bit of improvements in the back end (metal traces). That aside, if foundries adopted say a 1T-1C SRAM we’d see a pretty rapid density doubling
Is 1T1C SRAM a technological thing or does it mean "persuade designers to use DRAM in the many cases where the retention contract could be timeboxed with a bit of extra thought and cross-team haggling"?
Is the increase in wafer cost higher than the density increase? If so, that means that the cost per transistor is also going up.
It's hard to tell because AI has pushed up costs. IE. Chip fab margins are increasing.
But generally, I think it's even or increasing $/transistor for each node. I'd guess that A14 would have been 20% more expensive than N2 regardless or AI or not.
It probably is still worth it because you're also getting 20-30% better power efficiency - which is a big deal for data center chips.
Come on we're in the 21st century, UTF-8 is pervasive. Just call it "Å14" node.