I seem to remember that Alpha’s were very fast for the time but their maximum optimization level waived IEEE floating point conformance. This, of course, drove us nuts trying to validate ports of numerically intensive code. Less interesting chips with lower optimization and limited market penetration.
Now, HP’s PA-RISC chips…. Those things were fast and easier to work with. Curiously, with SoftPC they could do windows faster than a 486 could. Slaughtered all sorts of mini-supers they did.
Would have been interesting if alpha survived to compete with SGI’s MIPS.
I worked on the first PA-RISC workstations (“snakes”, 1989-1991). PA-RISC started as a fairly pure RISC design and was consequently very simple and predictable (short pipeline, 1 delay slot, no complex instructions). The philosophy of the design team was to make the system fast with high clock speeds, short pipelines, and big caches, all big fundamental variables in the performance equation.
Alpha was much more sophisticated but also a lot more complex. The Alpha memory model, in particular, was quite complex with lots of cache control and barrier primitives, IIRC. But it could fly when you got the stars to align.
Edit: Alpha also came out later and PA-RISC also got more complex in later generations.
I feel like PA-RISC actually landed with a handful of useful somewhat-complex instructions. It always struck me as the best architecture from that era, making the correct trade-off of avoided microcode but adopted stuff like completers and shift-and-add operations to minimize instruction count and maximize work done per pipeline.
what did they not implement from 754? Given the design of the processor i can imagine them being very aggressive with assumptions around exception handling / traps - iirc this is actually the original reason why Tomasulo algorithm exists because the first out-of-order processors didn't actually make any guarantees about the order that you would observe these side effects.
Alpha punts handling of denormals, infinities and NaNs to software emulation, but that wasn't particularly unusual: some sparc CPUs and early implementations of Arm VFP floating point did the same.
Looking at the alpha architecture manual, the fp emulation traps are imprecise, which imposes constraints on codegen to make it work right: the "trap shadow" extends from the potentially trapping insn until a following trap barrier, and in the shadow you mustn't e.g. use a register more than once as a destination, have a branch, or modify registers that are inputs to any insns in the shadow. (The idea is that the hardware will have already executed some of the insns in the shadow by the time it realises it needs to trap, and the handler has to be able to emulate the trapping insn and resume execution at the insn just after that, so it will re-execute all the insns in the shadow.) That's obviously pretty inconvenient for codegen, so I wouldn't be surprised if the compiler provided some kind of fast-math mode where it didn't trap and you just had to avoid generating denormals, infinities, etc.
I think making the fp using code have to be written carefully to work with the software emulation of edge cases is unusual -- I don't think either sparc or arm imposed that requirement, and instead trap precisely, or at least before anything happens where it would matter that the fp insn is emulated late.
> David Jessel, the Alpha's senior product manager, claims that Alpha fans have nothing to worry about. "Compaq has been fully supportive of the Alpha and is continuing to invest in it," Jessel said.
That worked out swimmingly for Alpha... >sigh<
I never programmed Alpha assembly, so I don't really have a feel for the architecture. I did deploy some Alpha-based boxes running NT, and they were very nice. They didn't feel pieced-together like x86 servers did.
On the hardware side, DEC built very-well engineered hardware. The early Alpha machines were very well designed. Even the PC compatible lines of the era were built to a very high quality standard.
Without AMD rescuing x86, PowerPC wouldn't have died. MIPS wouldn't have died, and faces with the need to brake the 4Gn barrier on consumer equipment microsoft would have had windows running on three or four competing architectures until 2013 when everything would have switched to ARM.
A video of an 1994 presentation put together for Hot Chips VI on the 21164: https://youtube.com/watch?v=OHupqMbLj1g
An April 1992 University Video Communications presentation on the Alpha architecture https://youtube.com/watch?v=klg1FtHADso and then from 38m 19s on the 21064 CPU https://youtube.com/watch?v=klg1FtHADso&t=2299s . From about 2m52s https://youtube.com/watch?v=klg1FtHADso&t=172s to 4m 43s Richard L. Sites gives the Alpha team’s predictions from 1992 for the next 12-25 of CPU development, which seem to have been fairly on the nail.
(Sites hasn’t been idle recently either! He’s responsible for the ultra-low-overhead KUTrace: https://news.ycombinator.com/item?id=40972099 )
I seem to remember that Alpha’s were very fast for the time but their maximum optimization level waived IEEE floating point conformance. This, of course, drove us nuts trying to validate ports of numerically intensive code. Less interesting chips with lower optimization and limited market penetration.
Now, HP’s PA-RISC chips…. Those things were fast and easier to work with. Curiously, with SoftPC they could do windows faster than a 486 could. Slaughtered all sorts of mini-supers they did.
Would have been interesting if alpha survived to compete with SGI’s MIPS.
I worked on the first PA-RISC workstations (“snakes”, 1989-1991). PA-RISC started as a fairly pure RISC design and was consequently very simple and predictable (short pipeline, 1 delay slot, no complex instructions). The philosophy of the design team was to make the system fast with high clock speeds, short pipelines, and big caches, all big fundamental variables in the performance equation.
Alpha was much more sophisticated but also a lot more complex. The Alpha memory model, in particular, was quite complex with lots of cache control and barrier primitives, IIRC. But it could fly when you got the stars to align.
Edit: Alpha also came out later and PA-RISC also got more complex in later generations.
I feel like PA-RISC actually landed with a handful of useful somewhat-complex instructions. It always struck me as the best architecture from that era, making the correct trade-off of avoided microcode but adopted stuff like completers and shift-and-add operations to minimize instruction count and maximize work done per pipeline.
VAX compatibility was very important to DEC- the Alpha has hardware to handle the non-IEEE VAX floating point formats.
what did they not implement from 754? Given the design of the processor i can imagine them being very aggressive with assumptions around exception handling / traps - iirc this is actually the original reason why Tomasulo algorithm exists because the first out-of-order processors didn't actually make any guarantees about the order that you would observe these side effects.
Alpha punts handling of denormals, infinities and NaNs to software emulation, but that wasn't particularly unusual: some sparc CPUs and early implementations of Arm VFP floating point did the same.
Looking at the alpha architecture manual, the fp emulation traps are imprecise, which imposes constraints on codegen to make it work right: the "trap shadow" extends from the potentially trapping insn until a following trap barrier, and in the shadow you mustn't e.g. use a register more than once as a destination, have a branch, or modify registers that are inputs to any insns in the shadow. (The idea is that the hardware will have already executed some of the insns in the shadow by the time it realises it needs to trap, and the handler has to be able to emulate the trapping insn and resume execution at the insn just after that, so it will re-execute all the insns in the shadow.) That's obviously pretty inconvenient for codegen, so I wouldn't be surprised if the compiler provided some kind of fast-math mode where it didn't trap and you just had to avoid generating denormals, infinities, etc.
I think making the fp using code have to be written carefully to work with the software emulation of edge cases is unusual -- I don't think either sparc or arm imposed that requirement, and instead trap precisely, or at least before anything happens where it would matter that the fp insn is emulated late.
600Mhz Alphas existed when there was 195mhz MIPS
Fun fact - Linus first trip to the United States was related to Linux-on-Alpha port and sponsored by Digital Equipment Corporation.
It’s so good to re-read Tom Halfhill’s articles. I wonder where he’s been in the past… checks notes… 30 years I haven’t seen his writings.
> David Jessel, the Alpha's senior product manager, claims that Alpha fans have nothing to worry about. "Compaq has been fully supportive of the Alpha and is continuing to invest in it," Jessel said.
That worked out swimmingly for Alpha... >sigh<
I never programmed Alpha assembly, so I don't really have a feel for the architecture. I did deploy some Alpha-based boxes running NT, and they were very nice. They didn't feel pieced-together like x86 servers did.
On the hardware side, DEC built very-well engineered hardware. The early Alpha machines were very well designed. Even the PC compatible lines of the era were built to a very high quality standard.
My understanding is that after Compaq sold the Alpha IP to intel, and quite a lot of the DNA ended up in Nehalem and Sandy Bridge.
Not sure about that bit...
What is well known however, is that a bunch of Alpha engineers wound up at AMD, and a lot of that DNA went into the OG Athlon
From back when IA-64 (A.K.A. Itanium) was supposed to take Intel to the promised land.
Without AMD, maybe it would have.
No, it wouldn't have.
Without AMD rescuing x86, PowerPC wouldn't have died. MIPS wouldn't have died, and faces with the need to brake the 4Gn barrier on consumer equipment microsoft would have had windows running on three or four competing architectures until 2013 when everything would have switched to ARM.
Itanium would have already been a rotting corpse.
AMD rescued Intel from its own management.
I remember Byte folding, but I’d blanked that it was a full 28 years ago.