FWIW, I wouldn't be surprised if you only have a couple threads using this at a time max since it looks an awful lot Apple's AMX/SME stuff. Those Apple execution units only have single engines shared about per cluster.
XSAVE lets you not bother saving register state that user space hasn't changed at the granularity of each large feature.
Great article. What does the (organizational) process look like to convert one of these specs to a processor product, does it go through a committee like the C++ standards?
> AMD, in partnership with Intel and the x86 EAG (Ecosystem Advisory
Group) [EAG24], is readying ACE as the standard matrix acceleration architecture for x86, further enhancing the already
vibrant x86 ecosystem.
I assume Zen 6 won't support these, so we are looking Zen 7 at the earliest, which is 2028 earliest.
In the meantime x86 don't have much in the roadmap that compete well with ARM vendor's offering. And that was before Nvidia decided to join the fight.
AI Compute Extensions, ACE.
With 8kb of registers for just this one feature, what does a modern process-control-block look like?
On x86, basically whatever XSAVE writes out.
FWIW, I wouldn't be surprised if you only have a couple threads using this at a time max since it looks an awful lot Apple's AMX/SME stuff. Those Apple execution units only have single engines shared about per cluster.
XSAVE lets you not bother saving register state that user space hasn't changed at the granularity of each large feature.
Great article. What does the (organizational) process look like to convert one of these specs to a processor product, does it go through a committee like the C++ standards?
> AMD, in partnership with Intel and the x86 EAG (Ecosystem Advisory Group) [EAG24], is readying ACE as the standard matrix acceleration architecture for x86, further enhancing the already vibrant x86 ecosystem.
Source: https://x86ecosystem.org/wp-content/uploads/2026/03/ACE-Whit...