The biggest issue is simply: an HDL is not a programming language.
As such, making an HDL look like a programming language doesn't increase my expressiveness or productivity all that much. (Side note: this assumes VHDL or SystemVerilog--old-school Verilog is terribly anemic in ways that SystemVerilog mostly fixed)
Now, my testbench, on the other hand, is dramatically helped by being in a real programming language with the appropriate constructs. However, we already have cocotb (in Python!) which fits the bill there and interfaces directly with my simulators without a translation step.
While Amaranth is notably Python-for-hardware, I think the real standout feature is that it all but eliminates the infamous simulation-vs-synthesis mismatch. Verilog can simulate perfectly yet explode in synthesis, but Amaranth omits non-synthesizable constructs and enforces explicit instantiation. The result: a design that passes simulation is far more likely to synthesize identically, averting costly back-end surprises. If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas, that philosophy alone makes Amaranth worth a look.
> If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas
This is LLM phrasing. It's trying to be witty and relatable about an experience basically no person has ever had - or at least, those people being hardware engineers, they usually don't try to be witty and relatable in forum comments.
I don't know though, the comment as a whole doesn't feel AI-generated, but maybe AI-assisted.
It's been a while since I've done this stuff, but VHDL seemed like this to me: that generally if it compiles, it synthesises. I really battled with Verilog!
The biggest issue is simply: an HDL is not a programming language.
As such, making an HDL look like a programming language doesn't increase my expressiveness or productivity all that much. (Side note: this assumes VHDL or SystemVerilog--old-school Verilog is terribly anemic in ways that SystemVerilog mostly fixed)
Now, my testbench, on the other hand, is dramatically helped by being in a real programming language with the appropriate constructs. However, we already have cocotb (in Python!) which fits the bill there and interfaces directly with my simulators without a translation step.
While Amaranth is notably Python-for-hardware, I think the real standout feature is that it all but eliminates the infamous simulation-vs-synthesis mismatch. Verilog can simulate perfectly yet explode in synthesis, but Amaranth omits non-synthesizable constructs and enforces explicit instantiation. The result: a design that passes simulation is far more likely to synthesize identically, averting costly back-end surprises. If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas, that philosophy alone makes Amaranth worth a look.
It appears that your entire profile is simply LLM generated comments, including this comment right here. Please do not do this on HN.
The parent comment absolutely has the LLM stench.
Appears? How so?
> If you've ever been burned by Verilog's "works in sim, breaks in synthesis" gotchas
This is LLM phrasing. It's trying to be witty and relatable about an experience basically no person has ever had - or at least, those people being hardware engineers, they usually don't try to be witty and relatable in forum comments.
I don't know though, the comment as a whole doesn't feel AI-generated, but maybe AI-assisted.
Amaranth is basically SystemC but in Python (and it's much easier to use and works better)
It's been a while since I've done this stuff, but VHDL seemed like this to me: that generally if it compiles, it synthesises. I really battled with Verilog!
But what is it for? It would be impressive if they used this to develop their gravitons but I find that hard to believe. What's the use case?
https://glasgow-embedded.org/
Which uses a single Python codebase to implement both the gateware (as Amaranth) and the software which interacts with it.
https://greatscottgadgets.com/cynthion/ is another in-production user of it, a USB protocol analyzer and tool.