What's interesting is that these devices don't need 321+ litho steps; the vertical layers are all defined with deposition. Lithography step count isn't layer dependent it seems.
What does 'layer' mean in this context? I'm only familiar with planar style logic process nodes which have maybe up to 20 layers (and many more lithography steps to manufacture those layers), but completely ignorant of how the term is used for a flash process node.
How many layers are needed for each physical (MLC/TLC/QLC) cell?
Is it 1,2, or a lot more? Is this effectively 320 cells stacked vertically, or e.g. 40, and some planar style logic at the bottom of the stack (say another 10 layers)
I'm assuming that this might then be packaged up to e.g. 16 silicon dies deep with through-silicon-vias, so could a cross section of a package actually have 5000 layers, or am i double counting here?
Whatever this numbers are I still find this amazing that it is economical and/or functional!
This is 321 physical layers of silicon in an IC, not 321 charge levels.
QLC flash - with 16 charge levels, for four bits per cell - is pretty common nowadays, but that's as far as it goes so far. And stability is indeed a concern; modern flash devices rely heavily on error correction.
But they aren't high capacity. As far as I've seen, we've been stuck on the same XY size 512 Mb dies for over a decade. Even now, Infineon is claiming they have a series that'll go up to 4 Gb but is still at the standard 2 Gb maximum. NOR hasn't gotten any denser in forever.
What's interesting is that these devices don't need 321+ litho steps; the vertical layers are all defined with deposition. Lithography step count isn't layer dependent it seems.
https://youtu.be/ANHzVOiUwGI
https://thememoryguy.com/3d-nands-impact-on-the-equipment-ma...
What does 'layer' mean in this context? I'm only familiar with planar style logic process nodes which have maybe up to 20 layers (and many more lithography steps to manufacture those layers), but completely ignorant of how the term is used for a flash process node.
How many layers are needed for each physical (MLC/TLC/QLC) cell? Is it 1,2, or a lot more? Is this effectively 320 cells stacked vertically, or e.g. 40, and some planar style logic at the bottom of the stack (say another 10 layers)
I'm assuming that this might then be packaged up to e.g. 16 silicon dies deep with through-silicon-vias, so could a cross section of a package actually have 5000 layers, or am i double counting here?
Whatever this numbers are I still find this amazing that it is economical and/or functional!
When I was in school studying NAND devices (2004-2010) we were quite apprehensive at the long term quantum stability of 4-layer devices.
This (the past 20 years of improvement) is an incredible feat of engineering.
This is 321 physical layers of silicon in an IC, not 321 charge levels.
QLC flash - with 16 charge levels, for four bits per cell - is pretty common nowadays, but that's as far as it goes so far. And stability is indeed a concern; modern flash devices rely heavily on error correction.
> triple level cell-based 4D memory
What does 4D memory mean?
It’s marketing speak. 3D flash (stacked chips) with the control circuits stacked underneath instead of to the side. So it’s one louder.
https://www.tomshardware.com/news/sk_hynix-debuts-4d_nand,37...
Nothing - just marketing. It's their 2nd gen Periphery Under Cell (PUC) device.
Bigger number = more betterer
I just want smaller SPI flash for embedded :( it's been over 10 years since there's been improvement in that space
WLCSP-8 is pretty damn small already, at ~1.5mm square. Hard to get much smaller.
But they aren't high capacity. As far as I've seen, we've been stuck on the same XY size 512 Mb dies for over a decade. Even now, Infineon is claiming they have a series that'll go up to 4 Gb but is still at the standard 2 Gb maximum. NOR hasn't gotten any denser in forever.
What's the use case for a NOR flash that large? Even at 2 Gbit, you're probably better off with something optimized for density like eMMC.
Cookie permission dialog is the worst I have encountered in months
Thank god for ublock origin filters, i have all the optional filter lists, I never see those things. EVER.
Where’s the point where you figure out how to stack chiplets perpendicular to a backplane instead of doing lithography 300 times on the same chip?
That's kind of what we're doing already, although the stacking is parallel, not perpendicular. A lot of the innovation is in how the dies are tied together, cf. https://www.anandtech.com/show/9520/toshiba-brings-throughsi...
This is an interesting testament to manufacturing reliability - that they can go to so many layers and still achieve good yield.
Wow. What's the yield like? Are some bits bad and bypassed during testing?
> Are some bits bad and bypassed during testing?
Always. All digital storage media depends on error correcting codes and sector-remapping these days.