I was following this discussion on the /r/chipdesign subreddit when Ken posted there a few days ago. Nice to see that he gave credit and linked to that thread.
I'm a physical design engineer that uses software from Cadence and Synopsys to do chip layout of blocks with billions of standard cells. Our flow automatically puts antenna diodes in for all block input pins. Then the tools are usually good enough to breakup internal nets with layer jumping to avoid antennas.
Some of the charge also comes from the CMP process. Modern chips have about 20 layers of metal but there are lots of other via layers in between those and then all the base layers with the actual transistors. You want the wafer to be flat before building the next layer.
Reading through, appears this is mostly a manufacturing concern that goes away once the chip is actually active. Correct? The charge buildup goes away, and then there's no further need for the diode antenna.
However, second question, does any chip actually use these for anything afterward? Or are these ever built so they actually do something other than simple provide manufacturing protection?
Example, they build up charge. So then the charge build up itself is effectively used as some form of remote communication method or channel between various portions of the chip. The diode discharges and in discharging effectively acts as some form of communication transfer.
Others, or it serves multiple purposes. One during manufacturing, one after manufacturing? Safety mechanism during manufacturing, and then the charge buildup location is oscillated, purposely charged, or used as a charge outlet for some other reason?
Others, Light Emitting Diode is, kind of by the name, a diode. Any of these that basically do blinking communication or something similar? Emits light when the charge breaks down, then that is picked up and used as data transfer?
Others, not going into extensively. Tune radio and TV receivers (varactor diodes). Generate radio-frequency oscillations (like actual antennas) (tunnel diodes, Gunn diodes, IMPATT diodes).
Basically, anything other than a safety mechanism for manufacturing?
You're correct that these are for manufacturing only. I've never heard of them being used for actual design purposes and that's probably because if you wanted an actual diode, you'd just use a "real" one.
Hi Ken! Your work is extremely interesting to me and I admire the effort your pour into these articles. It's been very cool to see your die analyses ramp up to more and more complex chips over the years. The Pentium is an especially neat target since it represents a major shift in the x86 architecture towards the modern chips we have today. Never a dull moment when I see a righto link!
Your pictures give insight into such a small world, individual freaking transistors on a CPU chip! Reading textbooks and wiki is one thing, but seeing silicon spliced up and photographed up close is another. Very interesting read, and very well presented too, thank you.
Chips seem to be around 25mm sq, and the smallest features around 10nm.
If you scaled up so the smallest feature is one mm then the chip would be around 2.5km square. (over 1.5 miles on each side)
If the smallest feature was about the width of human hair then divide the above by 100.
It’s precisely these orthogonal, secondary concerns that make every industry more difficult than people on the outside might think.
Articles like yours shed light on these challenges.
I’m reminded of a recent project working on a (small!) data warehouse where for the first time in my career I had to not only be concerned with theoretical performance of queries, such as the presence or absences of indexes, but orthogonal concerns such as the time taken to rewrite terabytes of data on disk during night ETL jobs… combining with the “change rate” of the source data.
Your article is a similar concern that only specialists in the in the industry are even aware of: it’s not enough to logically route connections — a challenging optimisation all by itself — but there are these competing physical optimisation issues as well that need to be simultaneously optimised!
> Note that when the chip is completed, every transistor gate is connected to another transistor's source or drain (which provides the signal to the gate)
That's a very curious assertion, which made me think a bit more (it feels incorrect at first but on a second thought it looks correct)
I would think of "pure input pins" but I suppose those have pull-up or pull-down "resistors" which in silicon are actually diodes? gateless fets?
Fun fact about "antennas" in chip manufacturing: They have nothing to do with actual antennas. Charge can build up on long wires during manufacturing because the chemicals involved are not neutral and have some interactions with exposed wires. That charge needs to go somewhere to protect the rest of the circuits. There's nothing RF about this.
Later technologies (28 nm and below) have extensive design rules around prevention of "antenna" effects.
I think that’s incorrect. The article and the Wikipedia page on the antenna effect say antenna effects are caused by plasma etching, which uses RF to create the plasma.
It's a bit confusing. The plasma is created by RF, but the RF doesn't cause the antenna effect (nor do "chemicals"). The charged ions and electrons in the plasma are what cause the charge buildup. The wire acts as an antenna in a metaphorical sense, not a literal sense, as I mentioned in Footnote 3.
While the discussion of IC architecture is doubtlessly interesting, I want to praise this page, and other pages on that site, for the photos of the circuits. Not only they are enlightening, they also have really great, soothing color palettes.
Indeed! A thought experiment I have some times is to imagine that every machine on the earth was destroyed overnight. We still have mines, people, books. How long would it take to get back to the level of industrialisation and science that would allow us to make (in this case) a 3 million transistor chip?
The vast majority of people have little idea of how much intellectual effort has gone into the current state of technology.
Perhaps decades. Perhaps thousands of years. It probably depends upon why those machines were destroyed. Look at World War II. European nations and Japan rebuilt relatively rapidly then rapidly built upon progress made during the war. On the other hand, we have the decline of the Roman Empire. While we may now acknowledge that the dark ages weren't as dark as our 19th century peers thought, the western world lost the will or the imagination to rebuild at large scales (which the semiconductor industry certainly is).
Indeed. A lady at a bar in Portland once inquired what I thought humanity’s most advanced technological achievement was, after a slight pause I said the modern microprocessor. She laughed in my face at the suggestion. But when I pressed her for an answer of her own, she refueled to say, instead would only insist that my answer was ridiculous. Odd lady.
Do we have the technology to automate reading of decapped chips so that we can reconstruct the logic, something like "OCR"? It seems like such a thing would be hard if it has to deal with all these weird details.
The antenna diodes are only relevant during manufacturing, when a metal line is connected on one end but not the other. ESD diodes on the other hand protect inputs against electrostatic discharge when the chip is in use.
There is a tiny amount of extra capacitance on the net because of the reverse-biased junction of the antenna diode, but that's it. These diodes do get taken into account in when determining timing though.
Very cool that this would be on the front page after I picked up a Pentium-75 from my local recycler today, it's an SX969. I can hold this chip in my hand and look up to see Ken's die shots. So cool! The ceramic package these Pentiums came in are pretty unique as well - it kind of sounds like setting a piece of glass down when I set the CPU on my desk.
That Pentium is the 80502, so it's almost the same as the one in my article except that it is built with 600 nm technology instead of 800 nm and it has 200,000 more transistors. It's easy to knock the lid off the package with a chisel if you want to see the die inside.
Now go look at the need for antenna diodes in SOI technology:) with the substrate no longer the safe haven, a lot more oxides can be exposed to large differential voltages during manufacturing.
I was following this discussion on the /r/chipdesign subreddit when Ken posted there a few days ago. Nice to see that he gave credit and linked to that thread.
I'm a physical design engineer that uses software from Cadence and Synopsys to do chip layout of blocks with billions of standard cells. Our flow automatically puts antenna diodes in for all block input pins. Then the tools are usually good enough to breakup internal nets with layer jumping to avoid antennas.
Some of the charge also comes from the CMP process. Modern chips have about 20 layers of metal but there are lots of other via layers in between those and then all the base layers with the actual transistors. You want the wafer to be flat before building the next layer.
https://en.wikipedia.org/wiki/Chemical-mechanical_polishing
Author here: I know this is a very obscure topic, but hopefully it will be interesting to some. Let me know if there are any questions...
Reading through, appears this is mostly a manufacturing concern that goes away once the chip is actually active. Correct? The charge buildup goes away, and then there's no further need for the diode antenna.
However, second question, does any chip actually use these for anything afterward? Or are these ever built so they actually do something other than simple provide manufacturing protection?
Example, they build up charge. So then the charge build up itself is effectively used as some form of remote communication method or channel between various portions of the chip. The diode discharges and in discharging effectively acts as some form of communication transfer.
Others, or it serves multiple purposes. One during manufacturing, one after manufacturing? Safety mechanism during manufacturing, and then the charge buildup location is oscillated, purposely charged, or used as a charge outlet for some other reason?
Others, Light Emitting Diode is, kind of by the name, a diode. Any of these that basically do blinking communication or something similar? Emits light when the charge breaks down, then that is picked up and used as data transfer?
Others, not going into extensively. Tune radio and TV receivers (varactor diodes). Generate radio-frequency oscillations (like actual antennas) (tunnel diodes, Gunn diodes, IMPATT diodes).
Basically, anything other than a safety mechanism for manufacturing?
You're correct that these are for manufacturing only. I've never heard of them being used for actual design purposes and that's probably because if you wanted an actual diode, you'd just use a "real" one.
Hi Ken! Your work is extremely interesting to me and I admire the effort your pour into these articles. It's been very cool to see your die analyses ramp up to more and more complex chips over the years. The Pentium is an especially neat target since it represents a major shift in the x86 architecture towards the modern chips we have today. Never a dull moment when I see a righto link!
Your pictures give insight into such a small world, individual freaking transistors on a CPU chip! Reading textbooks and wiki is one thing, but seeing silicon spliced up and photographed up close is another. Very interesting read, and very well presented too, thank you.
It'd be interesting to see how big a CPU chip scaled up to be big enough for a human to fit in (were it hollowed out) would end up being.
Reminds me of the Monster 6502. Not quite what you're suggesting, but still a large discrete monster of a board.
https://monster6502.com/
Instead of a hedge maze maybe we can have VR "walking through a 8086 or 8088" chip style maze in the future.
They're usually 150μm thick. Humans fit in about 300mm thick spaces, so you need 2000x linear scale.
Not to answer your question exactly but ...
Chips seem to be around 25mm sq, and the smallest features around 10nm. If you scaled up so the smallest feature is one mm then the chip would be around 2.5km square. (over 1.5 miles on each side)
If the smallest feature was about the width of human hair then divide the above by 100.
Absolutely fascinating!
It’s precisely these orthogonal, secondary concerns that make every industry more difficult than people on the outside might think.
Articles like yours shed light on these challenges.
I’m reminded of a recent project working on a (small!) data warehouse where for the first time in my career I had to not only be concerned with theoretical performance of queries, such as the presence or absences of indexes, but orthogonal concerns such as the time taken to rewrite terabytes of data on disk during night ETL jobs… combining with the “change rate” of the source data.
Your article is a similar concern that only specialists in the in the industry are even aware of: it’s not enough to logically route connections — a challenging optimisation all by itself — but there are these competing physical optimisation issues as well that need to be simultaneously optimised!
Great article!
> Note that when the chip is completed, every transistor gate is connected to another transistor's source or drain (which provides the signal to the gate)
That's a very curious assertion, which made me think a bit more (it feels incorrect at first but on a second thought it looks correct)
I would think of "pure input pins" but I suppose those have pull-up or pull-down "resistors" which in silicon are actually diodes? gateless fets?
Fun fact about "antennas" in chip manufacturing: They have nothing to do with actual antennas. Charge can build up on long wires during manufacturing because the chemicals involved are not neutral and have some interactions with exposed wires. That charge needs to go somewhere to protect the rest of the circuits. There's nothing RF about this.
Later technologies (28 nm and below) have extensive design rules around prevention of "antenna" effects.
I think that’s incorrect. The article and the Wikipedia page on the antenna effect say antenna effects are caused by plasma etching, which uses RF to create the plasma.
It's a bit confusing. The plasma is created by RF, but the RF doesn't cause the antenna effect (nor do "chemicals"). The charged ions and electrons in the plasma are what cause the charge buildup. The wire acts as an antenna in a metaphorical sense, not a literal sense, as I mentioned in Footnote 3.
While the discussion of IC architecture is doubtlessly interesting, I want to praise this page, and other pages on that site, for the photos of the circuits. Not only they are enlightening, they also have really great, soothing color palettes.
I'm fascinated by the fact that we study this 31 year old technology and are amazed by the complexity
Indeed! A thought experiment I have some times is to imagine that every machine on the earth was destroyed overnight. We still have mines, people, books. How long would it take to get back to the level of industrialisation and science that would allow us to make (in this case) a 3 million transistor chip?
The vast majority of people have little idea of how much intellectual effort has gone into the current state of technology.
Perhaps decades. Perhaps thousands of years. It probably depends upon why those machines were destroyed. Look at World War II. European nations and Japan rebuilt relatively rapidly then rapidly built upon progress made during the war. On the other hand, we have the decline of the Roman Empire. While we may now acknowledge that the dark ages weren't as dark as our 19th century peers thought, the western world lost the will or the imagination to rebuild at large scales (which the semiconductor industry certainly is).
Indeed. A lady at a bar in Portland once inquired what I thought humanity’s most advanced technological achievement was, after a slight pause I said the modern microprocessor. She laughed in my face at the suggestion. But when I pressed her for an answer of her own, she refueled to say, instead would only insist that my answer was ridiculous. Odd lady.
Do we have the technology to automate reading of decapped chips so that we can reconstruct the logic, something like "OCR"? It seems like such a thing would be hard if it has to deal with all these weird details.
Are the antenna diodes only there to reduce damage during manufacture or is there also impact runtime in an electromagnetic noisy environment?
The antenna diodes are only relevant during manufacturing, when a metal line is connected on one end but not the other. ESD diodes on the other hand protect inputs against electrostatic discharge when the chip is in use.
There is a tiny amount of extra capacitance on the net because of the reverse-biased junction of the antenna diode, but that's it. These diodes do get taken into account in when determining timing though.
I thought they were there to allow Van Eck phreaking of the processor state
Very cool that this would be on the front page after I picked up a Pentium-75 from my local recycler today, it's an SX969. I can hold this chip in my hand and look up to see Ken's die shots. So cool! The ceramic package these Pentiums came in are pretty unique as well - it kind of sounds like setting a piece of glass down when I set the CPU on my desk.
That Pentium is the 80502, so it's almost the same as the one in my article except that it is built with 600 nm technology instead of 800 nm and it has 200,000 more transistors. It's easy to knock the lid off the package with a chisel if you want to see the die inside.
Now go look at the need for antenna diodes in SOI technology:) with the substrate no longer the safe haven, a lot more oxides can be exposed to large differential voltages during manufacturing.