EDRAM was very different, and IBM still uses it today. It is DRAM that is on the same die as the cores, which makes it far slower than AMD's VCache (which is SRAM). The concept is the same - putting a huge amount of cache on chip - but it's a very different solution.
The Intel solution was also not 3D stacked. It's a little like having an HBM stack next to the chip as a cache.
On mainframes, z14's drawer controller (that controlled four CPU sockets each) had a huge amount of eDRAM acting as an L4 cache for all cores in that drawer.
> It is DRAM that is on the same die as the cores,
From the article, it was actually a separate die/chiplets,
> Broadwell implemented its L4 cache on a separate 77mm2 die, creating a chiplet configuration. This cache die was codenamed “Crystal Well”, and was fabricated using the older 22nm process.
A lot of interesting details in article about how widely different this dram is, made to go fast fast fast. Fun read.
I'd really wanted a system with Crystal Well, seemed so cool. A lot of macs seemed to have the Intel Iris Pro models that had it. But general adoption in the PC market was - I feel - quite poor.
It was, at least, pretty good for video gaming: https://web.archive.org/web/20181025222235/https://techrepor... though, alas, it doesn't look like the Wayback Machine properly sucked up the whole article before the site got sold to particularly nasty link/content farmers.
EDRAM was very different, and IBM still uses it today. It is DRAM that is on the same die as the cores, which makes it far slower than AMD's VCache (which is SRAM). The concept is the same - putting a huge amount of cache on chip - but it's a very different solution.
The Intel solution was also not 3D stacked. It's a little like having an HBM stack next to the chip as a cache.
> and IBM still uses it today
On mainframes, z14's drawer controller (that controlled four CPU sockets each) had a huge amount of eDRAM acting as an L4 cache for all cores in that drawer.
If it's in the drawer controller rather than in the CPU, is it really 'e'?
Late HP-PA cpus had 1T-SRAM chips used for L2 cache to provide 32MB in PA-8800 and 64MB of L2 in PA-8900 (on top of still large 768kB L1i and L1d)
> It is DRAM that is on the same die as the cores,
From the article, it was actually a separate die/chiplets,
> Broadwell implemented its L4 cache on a separate 77mm2 die, creating a chiplet configuration. This cache die was codenamed “Crystal Well”, and was fabricated using the older 22nm process.
A lot of interesting details in article about how widely different this dram is, made to go fast fast fast. Fun read.
I'd really wanted a system with Crystal Well, seemed so cool. A lot of macs seemed to have the Intel Iris Pro models that had it. But general adoption in the PC market was - I feel - quite poor.
I believe the high cache skus were Mac exclusive.
They were also used in surface pros, not very effectively though since they were very thermally limited.
I don't think so. I had a Crystal Well laptop from MSI.
They also made them for desktop in I5, I7 and Xeon form.
There was at least one socketed version.
It was, at least, pretty good for video gaming: https://web.archive.org/web/20181025222235/https://techrepor... though, alas, it doesn't look like the Wayback Machine properly sucked up the whole article before the site got sold to particularly nasty link/content farmers.
(I miss Tech Report.)
"But I wonder if Intel could pull off high capacity caching sometime in the future"
The Xeon Max processors had up to 64GB of HBM that could act as memory or shadow external memory effectively acting like a huge L4 cache.
No Xeon 6 seems to have that feature, at least not for now. Xeon 6's top out at a paltry 504MBs of L3.