That neatly lines up with their actual GPU cores which are also 1024 bits wide (32 lanes of FP32) but I have no idea why they would need to go that wide in an auxiliary management core.
I noticed that as well, but it's still not obvious to me why, they must do a decent amount of complex computation on them.
Otherwise, they could've also used VLEN=128 with LMUL=8 to get effectively four 1024-bit vector registers.
Great news that I've never heard before. Good to know R5 has at least one friend with deep pockets. Wouldn't have guessed NVDA, who has been somewhat antagonistic to open computing.
These RISC-V cores are an internal implementation detail of their GPUs, so although the architecture is open they aren't really open in the sense that you can actually program them. Nvidia is doing it to save a buck because they no longer have to roll their own architecture (as they did previously) or pay for ARM licenses.
No making fun intended. I thought my tone was entirely factual.
You might also be interested to learn that at around the same time Western Digital announced a plan to switch all their (WD and SanDisk) disk controllers to RISC-V, at (then) a billion plus cores a year
Meh. They've spent a bunch of money engineering these but could have bought a microcontroller from the numerous companies for pennies. Yes, they have more than enough money to waste which is exactly what they have done here. If they have further plans for RISC-V, ie compete with ARM, AMD, Intel, Amazon, then that is something to cheer.
What really surprised me to learn is that use some VLEN=1024 RVV 1.0 cores: https://x.com/FlorianWoh/status/1848771326791848438/photo/3
That neatly lines up with their actual GPU cores which are also 1024 bits wide (32 lanes of FP32) but I have no idea why they would need to go that wide in an auxiliary management core.
I noticed that as well, but it's still not obvious to me why, they must do a decent amount of complex computation on them. Otherwise, they could've also used VLEN=128 with LMUL=8 to get effectively four 1024-bit vector registers.
Great news that I've never heard before. Good to know R5 has at least one friend with deep pockets. Wouldn't have guessed NVDA, who has been somewhat antagonistic to open computing.
These RISC-V cores are an internal implementation detail of their GPUs, so although the architecture is open they aren't really open in the sense that you can actually program them. Nvidia is doing it to save a buck because they no longer have to roll their own architecture (as they did previously) or pay for ARM licenses.
They're also not the SMs but the control processors - they're basically replacing esp32s with riscv based thingamajigs.
Nvidia talked publicly about this in May 2017, 7 1/2 years ago. No doubt they had already spent some time on it before that.
https://riscv.org/wp-content/uploads/2017/05/Tue1345pm-NVIDI...
https://xkcd.com/1053/
No making fun intended. I thought my tone was entirely factual.
You might also be interested to learn that at around the same time Western Digital announced a plan to switch all their (WD and SanDisk) disk controllers to RISC-V, at (then) a billion plus cores a year
https://www.anandtech.com/show/12133/western-digital-to-deve...
And in December 2019 Samsung announced that there are two SiFive RISC-V cores in each Galaxy S20 (and presumably the matching Galaxy Tab)
https://www.anandtech.com/show/15228/samsung-to-use-riscv-co...
Just a few heavyweights using -- and announcing! -- using RISC-V in the times before most people had heard of it.
Meh. They've spent a bunch of money engineering these but could have bought a microcontroller from the numerous companies for pennies. Yes, they have more than enough money to waste which is exactly what they have done here. If they have further plans for RISC-V, ie compete with ARM, AMD, Intel, Amazon, then that is something to cheer.
Announced during Nvidia's presentation at this year's RISC-V Summit.